The present invention relates broadly to semiconductor memory devices, and in particular to a fast access non-volatile MNOS memory apparatus.
In memory circuits utilizing variable threshold devices, such as MNOS transistors, the threshold value at which the transistor conducts may be controlled by having a low threshold level to supply a logic or binary "one", and by having a high threshold level to supply a logic or binary "zero". In such circuits, it is desirable to have a short write cycle time to enable fast writing of data into the memory cell as well as reading data out. In a prior art MNOS memory circuit, data may be written into the memory cell over and over. In other words, the memory cell may be written as a binary one for a number of times in a row before a binary zero is written. This causes the variable threshold transistor to shift its threshold between high and low to the maximum extent during the write cycle which saturates the device to a condition, which may be referred to as the saturated threshold state. Thus, when it is desired to write a binary level of the opposite state into the memory cell, the write pulse must have adequate polarizing voltage and time to shift the threshold voltage of the transistor from the previous saturated state. To speed up the time of writing a binary level or shifting the voltage in a variable threshold transistor such as an MNOS transistor, the voltage or electric field across the gate insulator of the device is increased by increasing the polarization voltage. Unfortunately, these high electric fields across the gate insulator of the MNOS device during the write cycle serve to accelerate the undesirable endurance phenomena creating a smaller threshold voltage and decreased retention time of the memory state.